One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the non-addressed columns or rows of the array, respectively, also becomes very large. While the leakage current through any one non-addressed diode on the selected row or column will have little impact on the operation of the device, the cumulative leakage through multiple thousands of non-addressed diodes can become significant. This aggregate leakage current can become great enough that the output voltage or current or charge can be shifted such that the threshold for distinguishing between a one state and a zero state of the addressed diode location can become obscured and can result in a misreading of the addressed diode location. Furthermore, as the arrays are scaled to smaller and smaller geometries, the semiconductor structure can become a limiting factor in that the layers of semiconducting material must be kept thick enough to control reverse leakage currents; however, to further reduce the scale of the devices the thickness may also have to be reduced to facilitate such scaling.
In a diode array storage device, a bit is addressed by selecting one row through the array and one column through the array whereby said selected row and column intersect at said bit. If the rows are the array dimension to which the storage diode anodes are connected and the columns are the other array dimension to which the storage diode cathodes are connected, selection of a row is accomplished by applying a high voltage and selection of a column is accomplished by selecting a low voltage such that the diode at the point of intersection of the selected row and the selected column is forward biased. The non-selected rows and columns would have a voltage present such that a diode at the intersection of a non-selected row and a non-selected column would see a zero, a reverse, or a very small forward bias; the source of the non-selected rows and columns typically is high impedance or floating so as not to induce or enable significant leakage currents. The binary state of the addressed bit is determined by the presence or absence of a current path—if a low impedance current path is present it represents one logic state and if it is not (either no current path or a high impedance current path) the other logic state is represented. The bit is read at an output by either measuring the current flowing into the selected row line, column line or both (or into the entire array or a portion of the array) or by measuring the voltage on the selected row line, column line, or both or by extracting and measuring the charge remaining on the selected row line, column line, or both. In the case of the current measurement, a larger current reading would indicate the presence of a non-linear conductor at the addressed location. In the case of the voltage measurement, a convergence of the voltages applied to the selected row and selected column would indicate the presence of a non-linear conductor at the addressed location, and in the case of charge extraction, smaller remaining charge would indicate the presence of a non-linear conductor at the addressed location.
It must be noted that the selected row will typically have many diodes connected whose addressing is not intended and these diodes will often experience a slight forward bias and source a slight forward current to the non-selected columns. Likewise, the selected column will typically have many diodes connected whose addressing is not intended and these diodes will often experience a slight forward bias and sink a slight forward current from the non-selected rows. The extent of this current will be determined by the current paths existing within the array as a result of cumulative leakage currents of the many reverse biased diodes connecting the non-selected rows and non-selected columns. To minimize leakage, these diodes are typically made having multiple layers of semiconducting materials wherein some layers are made thicker to extend the depletion region of the device junction to reduce leakage currents. When the array is small, the cumulative leakage current is not a problem. But, when the array is very large, the cumulative leakage current can become great enough that the currents flowing in the non-addressed diodes on the selected row and selected column can become comparable to the current that would flow in an addressed diode if one is present. Since the current leaked in this manner is a function of the data stored in the array and the amount of leakage when reading any given bit can be different, it can be difficult to predict or compensate for this leakage. This makes it difficult or impossible to determine the cause of the current path and, consequently, the binary state of the addressed bit when the cumulative leakage current becomes too large. In many cases, the array can be divided into sub-arrays, but as the individual sub-arrays become large the problem returns.